Digole 2.6 Serial DS320240CIPS-66T SPI LCD Display Library for the PIC18F2550 XC8

The Pros: It’s color and it looks good even at steep angles. Getting a simple Hello, World app running is trivial. It’s engine is a PIC18F26K20! Oh, the price is pretty darn good. Buy 500 units (~$1000) and they’ll tweak the firmware.

The Cons: This isn’t the most stable platform. There isn’t a RAM based double framebuffer so it’s glacially slow. Oh, there isn’t even enough RAM to easily display a 320x240x16 image. The display doesn’t always turn on (needs a big cap). Documentation is incomplete and vague in sections. Video? Pu-leeze. AND I’ve had two shit-the-bed right after a 3.3V powerup. JUNK! Digole on feeBay fails to provide ANY response to questions – including a DOA module!

This library was derived from the Digole C source. Only cursory tests were performed due to a lack of time and both my modules are dead. The parts I need work well and compile much tighter than the original code. Most of the documentation is in the header file. If something is not as expected, or needs clarification please let me know.

Generate images to format here: http://www.digole.com/tools/PicturetoC_Hex_converter.php
Generate custom ug8 fonts here: http://www.digole.com/forum.php?topicID=330

I read on Digole’s message board that images can be a max of a miniscule 2064 bytes. I beg to differ, after displaying a 100×130, 26K image.

Four files are included:
Digole.h That’s right, the header file. (Psst! It’s an attachment below.)
Digole.lpp Yup, an XC8 library! (It’s another attachment.) Add the lib to your projects Library folder
Examples.c Oh, yeah, here comes the blinkly text
Configurationbits.h If you have to ask…

The example should work with most PIC18’s with little to no changes. Untested XC16 and XC32 libraries are available.

RC2 is for chip selection. If you use a different pin, make sure you redefine DigoleDisplaySelectPin in Digole.h.
SPI1! Remember when connecting the display…PIC SDO to Display Data and PIC SDI to Display SDO!

Oh, to that unoriginal jackass: Yes! This site is proudly run on a CMS! It’s a tool which works better than anything you can create, uh, plagiarize and call your own!

 * File:   pwm1_example.c
 * Author: Dave, of course
 * pic18f2550
 * Created on November 1, 2017, 12:51 AM
//Internal oscillator frequency for __delay_Xs()
#define _XTAL_FREQ  (250000UL)

#include "configurationbits.h"
#include   //You're going to crap out here because 1. there aren't <> or 2. there is an unwanted space after the xc
#include "Digole.h"

void main()
    //Configure pins as Input or Output
    TRISCbits.TRISC2 = 0; //Chip select
    TRISCbits.TRISC7 = 0; //SDO output
    TRISBbits.TRISB0 = 1; //SDI input ADCON1
    TRISBbits.TRISB1 = 0; //SCLK output ADCON1

    //Set pins high or low
    PORTCbits.RC7 = 0;
    PORTBbits.RB0 = 0;
    PORTBbits.RB1 = 0;        // SCK low    
    //SMP: Sample bit
    //SPI Master mode:
    //1 = Input data sampled at end of data output time
    //0 = Input data sampled at middle of data output time
    SSPSTATbits.SMP = 0;
    //CKE: SPI Clock Select bit(1)
    //1 = Transmit occurs on transition from active to Idle clock state
    //0 = Transmit occurs on transition from Idle to active clock state
    SSPSTATbits.CKE = 1;
    //CKP: Clock Polarity
    //1 = Clock inverted
    //0 = Clock not inverted
    SSPCON1bits.CKP = 0;
    //SSPEN: Master Synchronous Serial Port Enable bit
    //1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins. Must also TRIS ports and I and O
    //0 = Disables serial port and configures these pins as I/O port pins
    SSPCON1bits.SSPEN = 1;
    //SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits
    //0011 = SPI Master mode, clock = TMR2 output/2(3,4)
    //0010 = SPI Master mode, clock = FOSC/64(3)
    //0001 = SPI Master mode, clock = FOSC/16(3)
    //0000 = SPI Master mode, clock = FOSC/4(3)
    SSPCON1bits.SSPM = 0b0000;

    //Wait for slow ass display to post
    for (int i = 0; i < 6;i++)  
        DrawBox(200,200,40,40); //filled rect
        DrawCircle(200,130,30,0); //unfilled circle

        DrawCircle(180,150,20,1);//filled circle

        DrawFrame(190,10,50,30);//unfilled rect


 * File:   configurationbits.h
 * Author: Dave, of course
 * Comments:
 * Revision history: 

// PIC18F2550 Configuration Bit Settings

#pragma config PLLDIV = 1       // PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))
#pragma config CPUDIV = OSC4_PLL6// System Clock Postscaler Selection bits ([Primary Oscillator Src: /4][96 MHz PLL Src: /6])
#pragma config USBDIV = 1       // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)

#pragma config FOSC = INTOSCIO_EC// Oscillator Selection bits (Internal oscillator, port function on RA6, EC used by USB (INTIO))
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

#pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOR = OFF        // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
#pragma config BORV = 3         // Brown-out Reset Voltage bits (Minimum setting 2.05V)
#pragma config VREGEN = OFF     // USB Voltage Regulator Enable bit (USB voltage regulator disabled)

#pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

#pragma config CCP2MX = ON      // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
#pragma config LPT1OSC = OFF    // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)

#pragma config STVREN = OFF     // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
#pragma config LVP = OFF        // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

#pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
#pragma config CP1 = OFF        // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
#pragma config CP2 = OFF        // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
#pragma config CP3 = OFF        // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)

#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)

#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
#pragma config WRT2 = OFF       // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
#pragma config WRT3 = OFF       // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)

#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)

#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)

#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)


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